Micron used to produce some of the best RAM available to mainstream users through its Crucial brand. Despite the company's exit from the consumer market through its now-defunct Crucial brand, Micron had pledged to continue honoring warranties on existing Crucial products. A recent case on Reddit, however, highlights ongoing challenges with Micron's warranty process, where it reportedly offered a customer a ludicrouspayout for an RMA. Only after further communication did Micron provide an improved offer. Another user also chimed in with a similar story about an SSD return with Micron. We have reached out to Micron for comment.
Redditor Key_Tailor6948, who shared the email exchange with Tom's Hardware, recently shared their RMA experience with Micron's warranty process after encountering a failing memory module from a 48GB (2x24GB) DDR5 memory kit. While the Redditor did not specify the exact model of the memory kit, Crucial used to sell two such kits in this capacity: the Crucial Pro DDR5-6000 C48 and the Crucial Pro DDR5-5600 C46. The last known pricing for the memory kits was $489.99 and $459.99, respectively, during the memory shortage.
According to the Redditor, Micron allegedly said in an email that the company is no longer offering replacement products for warranty claims. Instead, Micron purportedly stated it would provide a refund based on the original purchase price, including taxes where applicable. However, the proposed refund amount was $241.86.
The major issue at hand is that the reimbursement Micron offered was based on the cost of the 48GB memory kit purchased before the recent memory shortage and the resulting price hikes. Nowadays, the most affordable 48GB DDR5 memory kit available on the market, such as a DDR5-6400 C32 one, which is faster than Micron’s discontinued offerings, starts at a staggering $649.99. The refund Micron proposed amounts to just 37% of the current market value for a somewhat comparable product. The Redditor's math about being 17% of market value and estimating similar-capacity memory kits going for “roughly $1,400" is a bit off based on verifiable pricing, but the proposed payment was still well short of current market value.
Beyond the disappointment over the low reimbursement, the Redditor expressed frustration that they had to send back the entire 48GB memory kit, even though only one of the two modules was faulty. This meant parting with a memory module that was still fully functional. Unfortunately, this is a common industry practice. Most manufacturers require the return of the full memory kit for warranty claims. It is exceedingly rare for companies to allow returns or replacements of only a single memory module from a multi-module kit, regardless of whether the other module is working perfectly. (EDIT 8/11/2026 : Micron's warranty states that it will either replace a product under warranty or refund the current market value of the product or the amount of the original purchase cost, whichever is lower. Therefore, Micron's offer is within the bounds of its warranty.)
The Redditor was also not happy about covering the shipping costs to return the defective memory module. This is another policy that varies widely among brands: some manufacturers cover all shipping fees, others split the cost, so you cannot really single out Micron in that aspect.
It would seem that Micron subsequently offered a more favorable resolution. The company agreed to send the user three Crucial Pro DDR5-6400 C32 16GB (CP16G64C32U5B) memory modules as a replacement. This solution matches the original capacity of 48GB and also delivers better performance than the user's original memory kit. The user accepted the offer.
Meanwhile, Crucial SSD owners are seemingly experiencing similar RMA practices from Micron. A Reddit user named LeanaIsTheBest highlighted in the same thread that Micron is allegedly refusing to provide direct replacements for a failing 4TB SSD. Instead, the company ostensibly offered a gift card equivalent to the original purchase price of the 4TB SSD as compensation. However, the company provided an alternate option to receive the same amount in cash through PayPal or Venmo, with the condition that the user pays the 6% transaction fee.
Micron wound down its consumer business back in December 2025. It is reasonable to think the chipmaker has reshaped its manufacturing factories to cater to more profitable markets, such as data centers and the AI sector. Micron probably is not maintaining inventory or production lines for consumer products, so direct replacements are unlikely. For a company that reported revenue of $41.46 billion in its last earnings call, it isn't a great look for Micron to not reimburse the replacement cost for loyal customers who have purchased its Crucial products.
The best RAM on the market generally utilizes integrated circuits (ICs) from industry giants such as SK hynix, Samsung, or Micron. Recently, however, Chinese chipmaker ChangXin Memory Technologies (CXMT) has emerged as a strong competitor amid the ongoing global memory shortage. In Colorful's latest overclocking exhibition, CXMT's ICs achieved speeds up to DDR5-8800 on AMD's X870E platform, keeping pace with the best overclocking ICs, such as SK hynix's A-die and M-die.
Many often regard CXMT as an underdog in the memory industry, particularly when compared to the "Big Three." Founded only a decade ago, the ambitious Chinese chipmaker eventually became China's largest domestic memory manufacturer and is now the fourth-largest memory maker globally.
The recent memory shortage has accelerated CXMT’s rise to fame. The chipmaker has been silently gaining ground in the memory market. Its momentum has been especially evident in the DDR5 segment despite the company having only unveiled its first DDR5 ICs in November 2025. Many top Chinese memory brands, including Asgard, Colorful, Gloway, and KingBank, are widely using CXMT ICs, and even Corsair has done so to a certain extent.
Colorful showed off an incredible overclock with its iGame Shadow II DDR5-6000 C34 memory kits, pushing both the 32GB (2x16GB) and 48GB (2x24GB) configurations far beyond their rated speeds. These kits reached DDR5-8812 and DDR5-8817, respectively, on Colorful's iGame X870E Vulcan W OC motherboard. Unfortunately, the screenshots provided by Colorful were too blurry to discern detailed specifications such as memory timings or DRAM voltage. For context, some high-end DDR5-8800 memory kits typically operate at timings around 42-55-55-140 with a voltage of 1.45V.
colorful igame shadow ii 16x2 kit (cxmt 2gb dies) reached 8800mhz mt100% on colorful igame x870e vulcan w oc (2dimm).reaching 8800 for 16x2 is very impressive and much harder to achieve compared to 24x2. based on the pattern we see with hynix dies, for example in z890 qvl, you… https://t.co/XzcS7SaJjV pic.twitter.com/g4aaQ3Q9SgAugust 6, 2026
The noteworthy aspect is that Colorful achieved the overclocking feat on 16GB memory modules. Most, if not all, DDR5-8600 and faster memory kits currently on the market come with 24GB memory modules. The reason is that many use SK hynix’s 24Gb (3GB) M-die ICs, produced on the chipmaker's advanced 1a-nm (~14nm) process node with Extreme Ultraviolet (EUV) lithography. These M-die ICs are the go-to choice for memory vendors thanks to their superior density, power efficiency, and ability to scale to higher frequencies.
In comparison, CXMT’s accomplishments are notable when considering the technological challenges. Due to U.S. export restrictions on China, CXMT does not have access to cutting-edge EUV equipment, so its 16nm node, which it uses for DDR5 ICs, leverages Deep Ultraviolet (DUV) machines instead. CXMT’s 16nm process is roughly in the same alley as the 1z nm (~14–15nm) nodes previously used by the Big Three, so CXMT is easily a few years behind the top-tier process nodes.
The reality is that CXMT will have to make do with what it has. The chipmaker is already developing a 1a-nm node but on DUV. It is far from prime time, though.
In addition to seeing CXMT ICs in mainstream memory kits, companies such as HP, Asus, and Acer have already started selling consumer devices, such as laptops or desktops with CXMT memory. Even Apple reportedly wants to buy memory chips from CXMT.
CXMT recently went public via IPO and saw its stock price skyrocket by 466%, raising over $8.6 billion. Without access to EUV machinery, CXMT will focus primarily on memory production and is rapidly building factories across China. The ambitious Chinese chipmaker hopes to steal 30% of the market share from the Big Three by 2030. It is just a matter of time before we start seeing CXMT ICs in all the prominent consumer memory brands.
Software performance expert, scientist, and GitHub developer Daniel Lemire compared historical computer memory prices and showed that decades of falling prices were undone in just a matter of months because of the massive demand for HBM. According to his X post, this event is a historical anomaly, and he cannot think of an instance where technology hardware prices reverted to levels from decades before.
On a historical basis, computer memory has been falling at an exponential rate for decades. But we just undid about 20 years of progress. RAM on a per unit basis is about as expensive as it was in 2007.To my knowledge, it is an historical anomaly. I cannot recall a similar… pic.twitter.com/UH6LgZ1fc4August 5, 2026
“RAM on a per unit basis is about as expensive as it was in 2007,” Lemire said. He also added, “I do not think anyone can predict what will happen, but I am guessing that we either find a way to build AI systems without so much memory, or we find really clever ways to make much more memory much faster.”
We also checked third-party data compiled and maintained by David Shim for theStanford DAM Project. The latest price for DDR5 memory sits between $13.28 and $11.41 per GB — the last time RAM hit this price was in 2008, when the price for DDR2 hovered by $15 and 11.00 per GB. These are based on nominal USD values, though. If we take 2024 inflation into account, the current amount for DD5 is between $12.74 and $10.94 per GB, which was last achieved in 2011, when DDR3 prices were at $11.85 per GB.
Technological advances, especially in manufacturing and miniaturization, meant that tech became cheaper over time. This has been true ever sincethe first general-purpose digital computer was created 80 years ago. ENIAC cost the government $400,000 in 1946, meaning it would probably cost around $6,850,297.44 today. However, its computing power equaled roughly 5,000 additions per second — by comparison, one of the cheapest smartphones you can get today, theMoto G Play, is on sale for $99.99. This smartphone is powered by a Snapdragon 680 processor with AI performance of 3.3 TOPS — that is 3.3 trillion operations per second. We can’t really compare the ENIAC to a modern processor, but it at least shows us the scale by which technology has advanced, and prices have dropped.
The massive increase in memory prices in recent times wasn’t caused by technological regression or a bottleneck in supply — instead, it’s themassive demand for HBM driven by the AI race. “The memory output is increasing by around 20% per year. Now, normally, that would be fantastically fast and amazing for any large, mature industry, but ask yourself, ‘Is the demand increasing by 20% a year?” Elon Musk said during the last SpaceX earnings call. “No, the demand is increasing by 200% a year, maybe higher.”
Other experts and industry leaders agree with Musk. The chairman of the SK Group, the holding company that owns memory chip manufacturer SK hynix, said thatRAM prices are “abnormally high,” and that the industry must take steps to increase supply and lower prices. Even RAM that uses chips from Chinese manufacturer CXMT, which some people look to as a cheaper alternative,generally tracked the prices of modules that use chips from the big three (Micron, Samsung, and SK hynix).
Aside from computers, other industries are already being affected by the shortage, includinggraphics cards,smartphones, gaming consoles, and evenautomobiles. We do not know how long the current memory crisis will last, but the situation is unsustainable and “something has to give.” The scary thing is that nobody knows what would happen if and when that time comes.
Ruling comes as part of second phase of landmark trial that found social media company enabled harm against users
A New Mexico court has ordered Meta, the parent company of Facebook, to pay $567m into a fund aimed at redressing adverse mental health impacts from the social media giant’s platforms.
The Thursday ruling comes as a part of the second phase of a landmark trial the social media giant lost in March. At the time, a jury found that the company knowingly harmed children’s mental health and concealed what it knew about child sexual exploitation on its platforms, and imposed the maximum penalty: a $375m fine.
In a striking reversal of traditional supply-chain dynamics, China’s ChangXin Memory Technologies (CXMT) has rebuffed Apple’s requests for lower prices on mobile DRAM, according to industry reports. The move underscores a severe shortage in general-purpose memory chips and hands greater negotiation leverage to South Korea’s Samsung Electronics and SK Hynix.
Apple had been exploring CXMT as a potential new supplier of LPDDR5X and other mobile DRAM for upcoming iPhones and smart devices, aiming to ease manufacturing cost pressures amid soaring memory prices. Sources indicate the iPhone maker sought further price reductions during negotiations. CXMT refused, instead holding firm at levels matching or even exceeding those charged by Samsung and SK Hynix.
The Chinese manufacturer’s bold stance stems from robust domestic demand. Companies such as Huawei and Xiaomi have locked in large volumes of CXMT’s DRAM through high-priced, long-term contracts. This push for supply-chain self-reliance has been intensified by ongoing U.S. semiconductor restrictions on China. With strong local orders secured, CXMT has little incentive to accommodate Apple’s stricter quality requirements or discount demands.
The episode highlights a broader market shift. Major memory producers have redirected significant wafer capacity toward high-bandwidth memory (HBM) to meet surging demand from AI servers and accelerators. This has sharply reduced output of conventional DRAM products like DDR5 and LPDDR5X, triggering a pronounced shortage—sometimes called “memflation” — and rapid price increases across the sector.Big tech firms that once used Chinese low-cost alternatives as leverage in annual pricing talks with primary suppliers now find that strategy ineffective. The low-cost “bypass” route has effectively closed, transferring pricing power from device makers to memory manufacturers.
For Samsung and SK Hynix, the developments create a favorable cycle. CXMT’s absorption of substantial Chinese commodity DRAM demand relieves the Korean firms of pressure to supply lower-margin general-purpose chips. They can instead prioritize higher-value AI memory products, including HBM4, LPCAMM2, and enterprise SSDs. Industry observers note that this positions the Korean companies with stronger control over global pricing in negotiations with major customers in the second half of the year.
One semiconductor industry source described the situation as unusual: CXMT is effectively supporting a floor under general DRAM prices while Samsung and SK Hynix consolidate leadership in premium AI memory. As a result, the Korean firms’ operating margins and market influence are expected to strengthen further.
Earlier this year, Apple had lobbied the U.S. government for clearer approval to source from CXMT, which appears on a Pentagon list of companies with alleged Chinese military ties. Memory cost pressures had already prompted Apple to raise prices on some Mac and iPad models. The latest reports suggest any potential deal with CXMT would not deliver the hoped-for cost savings.
MacDailyNews Take: The memory shortage is widely expected to persist well into 2027 and possibly beyond, as new fab capacity takes years to come online and AI-related demand continues to outpace supply growth. In this environment, the balance of power in the DRAM market has tilted decisively toward suppliers, particularly those focused on advanced, high-margin products.
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As NASA sets its sights on long-term exploration of the Moon and Mars, the agency is increasing the cadence of its Artemis missions. Helping bring these plans to fruition is Tom Percy, manager of systems engineering and integration for NASA’s Human Landing System Program.
Tom Percy, manager of systems engineering and integration for NASA’s Human Landing Systems Program, stands in front of an Apollo Program lander exhibit at the U.S. Space and Rocket Center in Huntsville near NASA’s Marshall Space Flight Center.
NASA/Charles Beason
Percy serves as a focal point in working with providers SpaceX and Blue Origin to accelerate and streamline systems designs, manufacturing, testing, and certification. He ensures the crewed landers that SpaceX and Blue Origin are developing for Artemis are designed, built, tested, and will operate with other NASA exploration assets safely and effectively.
“You might say that all human landing system integration work lands on my desk. And with the rest of my talented, hard-working systems engineering and integration team, we’re working to make it all happen,” Percy said.
A native of North Easton, Massachusetts, Percy earned a bachelor’s degree in mechanical engineering from the Rochester Institute of Technology in Rochester, New York, where he first got hands-on experience working on designs that could be applied to NASA’s sustainable lunar architecture.
“As an undergrad, I served as president of the Rochester Institute of Technology’s chapter of the American Society of Mechanical Engineers. To get some real-world engineering experience, we decided to participate in the Great Moonbuggy Race,” Percy said. “Now called the Human Exploration Rover Challenge, the competition is held annually at NASA’s Marshall Space Flight Center in Huntsville, Alabama.
“At the time, I had never heard of Marshall Space Flight Center,” said Percy. “But our student team designed and built a rover and traveled to Huntsville for the race. That’s when I learned about some of the projects in Marshall’s diverse portfolio that the center works for NASA. And that’s when I began planning to make my way to NASA Marshall for my career.”
Percy chose to move south and earn a master’s degree in aerospace engineering from the Georgia Institute of Technology in Atlanta. His research in the advanced propulsion lab and courses in space systems design culminated in a spacecraft design course and the chance to work directly with engineers at Marshall.
Since landing at Marshall in 2003, Percy has been involved in evaluating transportation architecture options for human deep space exploration, including missions to land astronauts on the Moon and Mars. He also has expertise in space transportation, including advanced propulsion technology development; trajectory analysis; and spacecraft and mission concept development. Percy earned a doctorate in aerospace systems engineering from the University of Alabama in Huntsville.
The range of experience comes together in his current role as manager of human landing systems engineering and integration.
“The world watched the amazing success of Artemis II. NASA and our commercial providers are looking forward to flying again soon and executing increasingly complex Artemis missions,” Percy said.
Through the Artemis program, NASA will send astronauts on increasingly complex missions to explore more of the Moon for scientific discovery, economic benefits, establish an enduring human presence on the lunar surface, and to build on our foundation for the first crewed missions to Mars.
Apple reportedly has around $1 billion in "processor wafers on the shelves awaiting packaging" amid ongoing memory shortages, putting pressure on the firm as it nears the launch of the iPhone 18. Tim Culpan of Culpiumsays Apple is "scrambling" for memory supply ahead of release, working with suppliers to get memory ready so it can finish packaging the A20 Pro and C2 chips that are reportedly inside the iPhone 18 lineup.
It's an interesting peek behind the curtain of the current supply chain limitations, which reach beyond simply DRAM chips. With fully-integrated SoCs across both desktop and mobile, Apple is uniquely vulnerable to supply chain limitations, not only in DRAM supply, but also in packaging capacity to bring together DRAM chips with processor wafers.
According to Culpan, Apple primarily sources DRAM from Micron, with smaller engagements from SK Hynix and Samsung. Micron (along with the other major memory players) has reportedly sold capacity for DRAM and HBM through 2027. A flurry of long-term agreements (LTAs) have cropped up over the past several months, guaranteeing supply to certain companies for several years.
The A20 Pro is the first chip to use TSMC's N2 process, and it has been progressing well, with TSMC reportedly sitting on around $1 billion worth of Apple wafers awaiting packaging with DRAM. Packaging happens with TSMC's new Wafer-Level Multi-Chip Module (WMCM) process, according to Culpan, which is similar to the CoWoS packaging but for mobile parts.
Culpan reports that "Apple and its assemblers remain confident that they can meet initial demand," but DRAM shortages could put pressure on shipments past the initial launch. Apple reportedly plans to ship around 200 million iPhone 18 units across the lineup throughout the device's lifespan. The iPhone 17 range saw record shipments last year, surpassing 245 million devices shipped in 2025.
This week, Samsung presented its vision for next-generation memory and storage solutions both for AI and general-purpose applications at the Future of Memory and Storage (FMS) 2026 conference. The company introduced zHBM, zNAND-O, and BV-NAND technologies at the event, and while they are aimed at very different applications, they share one common ingredient: they all rely on wafer bonding.
Here's a breakdown of each type of technology that the company announced.
zHBM: Samsung’s vision for custom HBM ultra-high-performance memory that will sit on top of logic dies.
zNAND-O: NAND memory that can be bonded atop a logic device to maximize bandwidth, reduce latency, and minimize power consumption.
BV-NAND (aka Samsung’s 10th Generation V-NAND): Samsung’s take on bonding NAND arrays atop all the circuitry needed to operate them. This is essentially next-generation 3D NAND technology that is used today by almost everyone, including Kioxia/Sandisk, SK Hynix, and YMTC (which was the first company to adopt such a method).
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zHBM: Placing HBM stack on top of logic
Around the time we first heard about HBM4's 2,048-bit interface, we read a 'semi-official' report that SK hynix and its partners were considering vertical integration of HBM4 stacks on top of logic chips. To a large degree, companies were considering installing these memory stacks on top of their processors as they doubted that it would be possible and feasible to use interposers to connect HBM4 stacks to AI accelerators. Over time, it turned out that integration of memory on top of logic is complicated when it comes to cooling, power delivery, and developing interposers that can handle a 2,048-bit memory interface. Samsung's zHBM appears to be a continuation of that effort.
(Image credit: Samsung)
Samsung's zHBM concept places HBM directly on top of an AI accelerator instead of on its perimeter, which greatly reduces the distance data must travel between compute and memory. The company says this architecture can increase bandwidth and power efficiency and projects that it can provide 8x the 'performance of HBM5', while its advanced wafer bonding is expected to enable over 10x higher memory density, 3x better energy efficiency, and more than 50% lower thermal resistance than HBM5.
While Samsung's claims about the zHBM look incredibly impressive, they are vague. For example, when the company claims that a 'next-generation interface system incorporating zHBM' will deliver 'approximately eight times the performance of HBM5,' it never explicitly states whether this refers to memory bandwidth, actual application performance due to a combination of improvements over standard HBM, or something else. Had Samsung intended to compare raw bandwidth, it would likely have used more precise wording, such as '8x higher bandwidth.'
Instead, the general term 'performance' may have many meanings. The same applies to references of improved power efficiency, higher memory density, and lower thermal resistance compared to HBM5, a standard that has not been fully defined or ratified. To make matters even more imprecise, Samsung mentions thermal resistance, which depends on implementation rather than the standard. Finally, Samsung didn't reveal which die stacking/bonding technology it will use for zHBM.
In any case, Samsung says that zHBM will also support customer-specific designs and will enable custom IP to be integrated into the interconnect layer (which plays a role similar to the base die, though it is definitely not a base die per se) between the HBM stack and the AI processor, which essentially means that zHBM is not necessarily an industry-standard solution, so it might be implemented with additional perks.
For now, Samsung hasn't disclosed any timeframes for when it plans to offer its zHBM solutions. The only clue is that it compares it to HBM5, which is likely to see the light of day sometime in the late 2020s or early 2030s.
zNAND-O(on-device): Put storage close to compute
Samsung also unveiled zNAND-O, a high-performance NAND memory currently in development that will enable putting four or eight stacks of NAND devices on top of logic dies. zNAND-O(n) device is based on the company's V-NAND platform (or rather, BV-NAND) and is meant to combine high storage density with improved I/O performance and low latency.
(Image credit: Samsung)
Samsung claims that the tech is suitable for edge AI systems running real-time, data-intensive inference workloads, though, of course, there are many other applications that can benefit from high-performance on-package storage.
(Image credit: Samsung)
Since the technology is in development, Samsung hasn't shared much information about it, even keeping the schematics of how it plans to put zNAND-O layers on top of a logic under wraps. We can speculate that since Samsung mentions 'improved I/O performance and low-latency,' it may be planning to exploit both the inherently parallel architecture of NAND memory with a high-performance interface, though we will not try to dive into details for the sake of not making the discussion too speculative.
BV-NAND: Good old V-NAND gets a new treatment
With BV-NAND, Samsung is essentially introducing a new brand name for its next-generation 3D NAND that bonds the NAND array on top of the I/O and logic wafer. This, in turn, produces the layer itself using high-performance logic process technologies and enables higher I/O speeds.
(Image credit: Samsung)
Samsung formally announced its 400-layer-class V-NAND (aka 10th Generation V-NAND) some time ago, and even disclosed that its areal density would be 28 Gb/mm2 with a maximum I/O speed reaching 5600 MT/s. This likely stipulates the usage of a pinout that is different from the 3D NAND packages used today. While the areal density of Samsung's 10th Gen TLC V-NAND is slightly lower when compared to that of Kioxia/Sandisk's BiCS10 TLC NAND, its maximum I/O speed is significantly higher, which perhaps justifies the new branding.
NAND Layer Counts
Samsung
Samsung
Sandisk/Kioxia
Sandisk/Kioxia
Kioxia/Sandisk
Micron
SK hynix
YMTC
YMTC
Generation
V10
V9
BiCS10
BiCS10
BiCS 8
Gen 9 (G9)
Gen 9
?
Xtacking 3.0/Gen 4
Layers
4xx-Layer
290-Layer (?)
332-Layer
332-Layer
218-Layer
276-Layer
321-Layer
232-Layer
232-Layer
Density
28 Gb mm^2
17 Gb mm^2
>37 Gb/mm^2
>29 Gb/mm^2
22.9 Gb mm^2 (?)
21.0 Gb mm^2
20 mm^2
>20 Gb mm^2
19.8 Gb mm^2
Architecture
TLC
TLC
QLC
TLC
QLC
TLC
TLC
TLC
QLC
Die Capacity
1 Tb
1 Tb
?
1 Tb
2 Tb
1 Tb
1 Tb
1 Tb
1 Tb
I/O Speed
Up to 5600 MT/s
Up to 3200 MT/s
Up to 4800 MT/s
Up to 4800 MT/s
Up to 3600 MT/s
Up to 3600 MT/s
?
?
?
Considering the fact that Samsung rarely sells its memory to third parties and prefers to market client SSDs itself, a new brand for memory can be a sales driver, even if actual high-end drive performance is limited by a PCIe 5.0 x4 interface rather than by 3D NAND memory I/O. Then again, the performance of mid-range PCIe Gen5 SSDs that rely on a quad-channel NAND controller depends on 3D NAND I/O today, so marketing them under a new flash memory brand is a certain way to attract attention and then sell decent performance.
Samsung's new brand strategy
As the new name of the FMS tradeshow implies, the announcements touch upon very distinct industry needs. In the case of Samsung, we are talking about high-performance data center-grade AI accelerators; applications that need storage with latency that is lower than ~50 – 60 µs of modern high-end PCIe SSDs, though we will see how it compares to Z-NAND, and essentially a new generation of conventional 3D NAND with a new brand.
Except for the 400-layer-class Samsung BV-NAND that is set to hit the market in the foreseeable future, the company's new tech, like zHBM and zNAND-O, is years away.
Apple briefly removed Telegram from the App Store on Monday night after a review found content that violated its guidelines against child sexual abuse material (CSAM), but restored the app a short while later, according to Reuters.
It seems like this was a symbolic gesture. Removing the app didn’t affect any of the customers who had already downloaded it. Probably none of them saw the image. And restoring the app doesn’t mean that it’s completely free from CSAM—probably none of the major platforms is. It just means that Telegram did the obvious thing after the violation was reported, which presumably they would have done, anyway.
And before even contacting the developer? Telegram banning the account is what actually prevented users from potentially seeing the CSAM. Apple’s action seems like either a mistake or trying to send them a message.
I would note, by the way, that the Telegram app was apparently never removed from the Mac App Store. Which goes to show how little Apple cares about the Mac App Store.
Because Telegram quickly removes illegal content from public groups using all kinds of moderation tools, the attacker had to resort to a technical trick. He inserted AI-modified illegal content by editing an old message in an active group chat. As a result the content was effectively hidden from the group’s members, preventing them from seeing/reporting it.
The attacker was a takedown extortionist: someone who demands ransom from group owners in exchange for not targeting their communities. These extortionists use automated accounts to plant illegal content in public groups and then report it directly to Apple, attempting to trigger the removal of legitimate communities whose owners refused to pay them.
[…]
Extortionists have found a way to manipulate Apple into overreacting. Apple removed Telegram from the App Store before contacting us. This creates a potential systemic risk for every mobile app that hosts user-generated content. If an app used by more than a billion people can be removed from the App Store without prior warning, any app can be.
During the time the app was unavailable, many speculated that the move was politically motivated, or perhaps in response to the recent discovery that Telegram has allegedly been using an obfuscated private UIKit API to animate its emoji picker.
It’s sad but kind of hilarious that both of these so disparate theories were considered possible. Durov really does have political enemies, and Apple really does seem to have it out for Telegram. But, also, using private API to animate emojis totally seems like something that Telegram would do and that Apple would overreact to.
Over the last nine months, Mark Zuckerberg’s Meta has run dozens of paid ads that include explicit AI-generated child sexual abuse material (CSAM) and images of minors alongside sexually suggestive statements, according to details of the ads shared with WIRED. The ads, which in some cases reached several thousand accounts, were targeted at people living in the United States, United Kingdom, and more than a dozen European countries.
This is much worse than what happened with Telegram, yet Apple didn’t overreact.
Apple briefly removed Telegram from its App Store late on Monday after detecting child sexual abuse material (CSAM) in a public group. The messaging app was restored within about 40 minutes once Telegram deleted the content and banned the responsible user. Telegram CEO Pavel Durov later described the incident as the work of a “takedown extortionist” who deliberately planted AI-modified illegal content to trigger the removal and pressure online communities.
According to Durov’s statement on X (see below), the attacker edited an old message in an active public group chat to insert the prohibited material. Because the edit was backdated, the content remained effectively invisible to ordinary group members, limiting their ability to report it through normal channels and helping it evade some of Telegram’s automated moderation tools. The perpetrator then reportedly flagged the material directly to Apple.
Durov characterized the actor as a takedown extortionist—someone who demands payment from group owners in exchange for not targeting their communities. These operators, he said, rely on automated accounts to seed illegal material in public groups and then report it to platform gatekeepers such as Apple in an effort to force the removal of legitimate communities whose administrators refuse to pay.
“From a practical standpoint, illegal pornographic content in Telegram’s public groups is not a systemic problem,” Durov wrote. “Our moderation is effective. The fact that attackers must resort to backdated, effectively invisible content and other technical tricks proves this.” He emphasized that Telegram routinely removes illegal material from public groups using a range of moderation tools.
Apple confirmed that a content review had identified CSAM that violated App Store guidelines. The company stated that Telegram “promptly removed the content and banned the user,” after which the app was returned to the store. Apple has not publicly addressed Durov’s claim that an extortionist manipulated the process. Durov noted that Apple pulled Telegram before contacting the company.
Durov framed the episode as a warning for other developers. “Extortionists have found a way to manipulate Apple into overreacting,” he said. “This creates a potential systemic risk for every mobile app that hosts user-generated content. If an app used by more than a billion people can be removed from the App Store without prior warning, any app can be.” He also cautioned that the tactics used by such coordinated reporting groups are evolving and that other platforms may be less prepared to identify and counter them.
The incident underscores ongoing tensions between large platforms that host user-generated content, the moderation challenges they face, and the policies of mobile app marketplaces that can unilaterally restrict distribution. Telegram continues to operate normally on iOS following the short-lived removal.
Last night Apple briefly removed Telegram from the AppStore because a user had planted illegal porn in a public chat.
Telegram was restored within hours. But I want to explain what happened — to warn other app developers and help protect online communities from similar attacks.
Because Telegram quickly removes illegal content from public groups using all kinds of moderation tools, the attacker had to resort to a technical trick. He inserted AI-modified illegal content by editing an old message in an active group chat. As a result the content was effectively hidden from the group’s members, preventing them from seeing/reporting it.
The attacker was a takedown extortionist: someone who demands ransom from group owners in exchange for not targeting their communities. These extortionists use automated accounts to plant illegal content in public groups and then report it directly to Apple, attempting to trigger the removal of legitimate communities whose owners refused to pay them.
From a practical standpoint, illegal pornographic content in Telegram’s public groups is not a systemic problem. Our moderation is effective. The fact that attackers must resort to backdated, effectively invisible content and other technical tricks proves this.
However, there are two important lessons here for app developers and online communities:
— Extortionists have found a way to manipulate Apple into overreacting. Apple removed Telegram from the App Store before contacting us. This creates a potential systemic risk for every mobile app that hosts user-generated content. If an app used by more than a billion people can be removed from the App Store without prior warning, any app can be.
— The tactics used by takedown extortionists are evolving, putting communities across social platforms at risk. Telegram has extensive experience identifying the tricks used by coordinated reporting gangs and protecting legitimate communities (even when doing so risks our own app being temporarily removed from the App Store). Other platforms may not be equally prepared.
Stay vigilant!
MacDailyNews Take: Apple’s App Store really is one of history’s most profitable cans of worms.
It’s an astonishing money machine: the broader App Store ecosystem facilitated over $1.4 trillion in developer billings and sales in 2025 alone. Physical goods and services (retail, food delivery, travel, etc.) made up the bulk (~$1.1 trillion), where Apple takes no commission. Digital goods and services accounted for about $149 billion, and in-app advertising another $151 billion. On the digital slice Apple typically charges 15–30%, generating many billions in high-margin revenue that helps power its Services business.
Yet the same walld garden that produces those results is a perpetual source of headaches. Apple’s near-total control over iOS distribution and payments has fueled years of antitrust battles — Epic Games, the U.S. DOJ, EU Digital Markets Act enforcement, court findings of non-compliance, and ongoing developer lawsuits. Critics call the commission the “Apple Tax,” complain about arbitrary review decisions, limited sideloading or alternative stores (outside certain regulated markets), and the risk that a single content flag can yank a major app offline without warning.
The recent Telegram episode fits the pattern perfectly. A brief App Store removal triggered by planted illegal content (which Telegram says was the work of a takedown extortionist) showed how Apple’s gatekeeper power can be gamed or lead to rapid, high-stakes reactions.
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The Cupertino-based tech giant told the FT it had moved in June to limit the high volume of requests it was receiving, with its review system coming under pressure from “AI slop” reports that can hallucinate security risks in its software.
Apple is grappling with an industry-wide phenomenon in which generative AI tools are transforming the cyber security arms race. This has produced both an increase in the detection of real security flaws and a wave of poor-quality submissions from amateur bug hunters using AI, the company said.
The shift in Apple’s approach was highlighted by Italian cyber security start-up Bynario, which told the FT it had used OpenAI’s ChatGPT to identify more than 50 bugs in the latest version of the Mac operating system in just three weeks. Among them was one of the most serious types of vulnerability—a privilege escalation exploit chain that could allow an attacker to seize full control of an Apple computer by gaining unrestricted access to the system.
“It is a very difficult time in the industry,” said Alfredo Pesoli, Bynario’s CEO and co-founder. “Maintainers and vendors have been flooded by the sheer amount of bugs [being found].”
Apple told the FT that it is now in contact with Bynario and reviewing its submissions. The company has introduced a cap and a 30-day cool-off period on submissions through its internal security portal, requiring users to request an increased quota. Each alleged security issue still requires human review to confirm, although Apple is also using AI internally to help triage the surge.
“With the growing volume of AI-generated security submissions across the industry, we recently adjusted the number of new reports a researcher can have open at once,” Apple said in a statement. Researchers can request an increase to that limit at any time to ensure critical reports reach its security teams.
MacDailyNews Take: Overwhelmed.
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It’s been a longtime feature of the annual Defcon hacker conference that attendees come away not only with knowledge of new software vulnerabilities and hacking techniques but also an elaborately designed conference badge—often electronic masterpieces embedded with intricate puzzles, complex crypto challenges, hidden Easter eggs, and even the mechanical gear trains of a watch.
Each year’s badge creator endeavors to top previous designs and blow the minds of hard-to-impress hackers. But this year’s badges take a different tack. Instead of the badge designs being the star, it’s what is inside the hardware that will really stand out.
This year, Defcon asked legendary hardware hacker Andrew “bunnie” Huang to create the badges—revealed here for the first time—and they include an innovative open source chip that Huang designed and that aims to do no less than advance the state of security, transparency, and trustworthiness in computing.
NASA, SpaceX Advance Wind Tunnel Tests for Starship Rocket
Engineers at NASA Ames conduct transonic and supersonic wind testing on a 1.2% scale model of the Super Heavy Version 3 rocket that will launch the Starship human landing system.
Credits: NASA
NASA and its industry partners are preparing for next year’s Artemis III demonstration mission by completing new wind tunnel tests on SpaceX’s Super Heavy Version 3 rocket booster. The tests, conducted at NASA’s Ames Research Center in California’s Silicon Valley, focused on better understanding the extreme aerodynamic forces the rocket can experience during re-entry. The recent test series builds on previous testing completed at NASA Ames in 2024.
NASA is working with SpaceX to develop the company’s Starship Human Landing System (HLS) to safely carry astronauts from lunar orbit to the Moon’s surface and back. The upgraded Super Heavy rocket booster is part of SpaceX’s Starship launch system. Version 3 of Starship and Super Heavy is expected to be the basis for the Starship HLS for Artemis III in 2027 and a later crewed lunar landing in 2028.
Engineers at NASA Ames conduct transonic and supersonic wind testing on a 1.2% scale model of the Super Heavy Version 3 rocket that will launch the Starship human landing system.
NASA
Engineers at NASA Ames conduct transonic and supersonic wind testing on a 1.2% scale model of the Super Heavy Version 3 rocket that will launch the Starship human landing system.
NASA
Engineers at NASA Ames conduct transonic and supersonic wind testing on a 1.2% scale model of the Super Heavy Version 3 rocket that will launch the Starship human landing system.
NASA
Engineers at NASA Ames conduct transonic and supersonic wind testing on a 1.2% scale model of the Super Heavy Version 3 rocket that will launch the Starship human landing system.
NASA
Although Starship HLS is a lunar lander designed and built by SpaceX, NASA collaborates with commercial companies to provide access to specialized testing facilities, like the wind tunnels at NASA Ames, and technical expertise, such as the team that set up the wind tunnel testing and helped analyze the results.
“NASA has a lot of experience with unsteady aerodynamics,” said Manish Mehta, discipline lead engineer for the HLS Plume and Aero Environments team, NASA’s Marshall Space Flight Center in Huntsville, Alabama. “We used the agency’s broad experience base of conducting wind tunnel tests for the space shuttle, the SLS (Space Launch System) rocket, and Orion spacecraft to efficiently set up and analyze the wind tunnel testing for the Super Heavy Version 3. In fact, similar testing at the Ames Unitary Plan Wind Tunnel resulted in adding strakes to SLS for Artemis II, so what we learned for Artemis II is helping us get to Artemis III and beyond.”
Testing
SpaceX’s Starship consists of a 33-engine first-stage Super Heavy rocket, or booster, and the second-stage Starship. Version 3 of Super Heavy incorporates many new and upgraded systems, including:
New propulsion systems and new Raptor 3 rocket engines
No engine section skirt, individual engine shrouds, or integrated large-scale base heat shield
Three gridfins on the Super Heavy booster instead of four, with each fin now 50% larger
An integrated hot stage replacing the previous single-use protective interstage
With significant changes to Super Heavy, NASA and SpaceX engineers wanted more information about the steady and unsteady aerodynamic forces the rocket will experience during atmospheric re-entry as it returns to the launch site for refurbishment and re-use.
“When a rocket, or an airplane, flies through air at high speed, it’s subjected to steady aerodynamic forces and moments, and unsteady aerodynamic forces and moments,” explained Jayanta Panda, unsteady aerodynamics subject matter expert at NASA Ames and part of the Human Landing System Plume and Aero Environments team. “An example of a steady aerodynamic force would be when air smoothly flows over the surface of the rocket as it ascends. An unsteady aerodynamic force would be air ‘buffeting,’ or hitting, certain areas the rocket at less predictable times and potentially causing vibrations.”
Wind tunnels
NASA and SpaceX used a 1.2% scale model of the Super Heavy Version 3 in the transonic wind tunnel and the supersonic wind tunnel at NASA Ames for testing. The transonic tunnel blasts scale models of rockets or aircraft with air at speeds ranging from Mach 0.2 to Mach 1.4 (Mach 1 is the speed of sound, or about 761 miles per hour). The smaller supersonic tunnel fires winds at higher speeds, from Mach 1.55 to Mach 2.5. The wind tunnel tests on Super Heavy Version 3, conducted in late 2025, used both tunnels to measure steady and unsteady air flows on the surfaces of Super Heavy.
“Resulting wind tunnel data on steady forces and moments helps predict how the rocket will react to forces in the atmosphere during re-entry so the flight software can effectively guide the rocket during flight,” Mehta said. “The unsteady pressure data helps engineers understand the environment around the rocket as it re-enters Earth’s atmosphere. Engineers use that information as one input into software that analyzes loads on the rocket.”
Through the Artemis program, NASA is returning humans to the Moon for scientific discovery, economic opportunity, to establish an enduring human presence on the lunar surface, and build the foundation for the first crewed missions to Mars – for the benefit of all.
The Company posted quarterly revenue of $109.4 billion, up 16 percent year over year.
[…]
“Today, Apple is proud to report our strongest June quarter ever, with double-digit revenue growth across iPhone, Mac and Services, and in every geographic segment,” said Tim Cook, Apple’s CEO.
You can’t argue with the strong iPhone and Mac sales figures, and Apple specifically called out the MacBook Pro and the MacBook Neo, which Cook said “has been especially popular” and suggested that the company is still struggling to make them fast enough.
It’s admirable (and sensible) that Cook isn’t pointing fingers at anyone but customers who want Apple products, but the key phrase in his statement is “the supply chain just has less flexibility in it than normal.” This is an acknowledgement that while in the past, Apple might have been able to boost chip production from its partners, today the chip industry is maxed out thanks to the wild building of chips for AI applications.
[…]
As an aside, Cook also alluded to reports that Apple has tried to get the U.S. government to authorize purchase of RAM from some forbidden Chinese chipmakers, which has aroused political ire.
Se colocou uma música menos conseguida num post antigo do Instagram ou se o áudio foi removido por direitos de autor, já não precisa de apagar a publicação. Saiba como trocar a banda sonora mantendo os gostos e os comentários.
There’s been a shift toward using a single DIMM of DDR5 to skirt the worst of the RAM pricing crisis. AMD has suggested to us previously, at least, that it’s an option PC builders are exploring, and it’s a wrinkle that’s shown up in dozens of prebuilts; one that we’ve been careful to avoid when recommending products, particularly during peak shopping events. But just how much gaming performance are you giving up with a single DIMM when using one of the best CPUs for gaming?
The conventional wisdom is that you’re giving up quite a bit of performance, resting on the ideas of previous DDR generations, where going down a single stick will cut your bandwidth in half. The same is true with DDR5, but things are a bit messier, which we’ll dig into later.
At a high level, using a single DDR5 DIMM doesn’t compromise gaming performance by nearly as much as you might expect. We saw drops of around 8% to 10% across Intel and AMD CPUs, and less than a 5% difference with AMD’s Ryzen 7 9800X3D.
A proper dual-channel configuration is still the way to go for optimal performance. However, our testing shows that even a single DDR5 DIMM offers superior performance to dual-channel DDR4 on CPUs that support both memory generations.
Using a single DIMM isn’t ideal, and it brings up compatibility issues if you plan on adding another DIMM down the line (another area we’ll touch more on in-depth later). But as a stopgap measure amid surging DRAM prices, a single DIMM of DDR5 holds up surprisingly well in gaming scenarios, and it represents a nice on-ramp into a DDR5 platform while prices are out of control.
Testing single-DIMM DDR5 in games
The geomean below speaks for itself. Moving down to a single DIMM drops some performance, but it’s not nearly as stark as I expected. There are some important notes about how we tested before dissecting the results, however.
As usual, we tested at 1080p with a mixture of High and Ultra settings, using Nvidia’s RTX 5090 Founder’s Edition to minimize the influence of the GPU. That’s even more important here, as we’re not evaluating CPUs but the memory that feeds the CPU. We're looking at a separate GPU and CPU here, as well; dual-channel memory is vital if you're using an iGPU.
We also wanted to create a realistic testing scenario. Assuming you’re going for a 2x16GB configuration, that means starting with a single 16GB DIMM, not a 32GB one. That’s what we did here. Our single-DIMM configurations run with just 16GB of memory, while dual-DIMM configurations run with 32GB. Capacity isn’t a major limitation for our testing here, though it will pose performance issues if you’re running several applications alongside your game.
(Image credit: Tom's Hardware)
The Ryzen 5 7600X was our biggest loser, dropping 10.9% of its average performance across our 13-game geomean with a single 16GB DIMM. The Core Ultra 7 270K Plus, meanwhile, dropped 8.7% of its average performance, while the Core i5-14600K similarly dropped 8.3% of its performance. The 1% lows are especially notable here, scaling with average performance rather than falling off a cliff.
Unsurprisingly, the Ryzen 7 9800X3D fared the best, dropping just 2.8% of its performance on average. As you’ll see through our individual game tests, the Ryzen 7 9800X3D shows identical performance with two DIMMs and a single DIMM in multiple games. The large and speedy L3 minimizes the impact of using a single DIMM, giving AMD’s 3D V-Cache CPUs another notch in their belt (as if they needed another).
Tom's HardwareTom's HardwareTom's Hardware
Our other geomeans don’t say much. A single-DIMM configuration consumes a few watts less, leading to slightly lower efficiency when balanced against the lowered performance.
(Image credit: Tom's Hardware)
007 First Light, the newest game in our test suite, shows good scaling across our test pool, so it’s a good place to start. The Core Ultra 7 270K Plus dropped 8.9% of its performance with a single DIMM, while the 9800X3D dropped 6.5%. The 14600K is worth highlighting here. A single DIMM lost us 7.9%, but that’s still better than dual-channel DDR4, and by a decent 6.8% margin.
(Image credit: Tom's Hardware)
This trend is fairly consistent, too. Starfield is punishing for single-DIMM configurations, with the 14600K losing 10.6% of its average performance. Even then, a single DDR5 DIMM is 6.9% faster than dual-channel DDR4. Intel platforms can scale up to high data rates, and we use 7,200 MT/s for Intel chips. With slower speeds, the performance will equalize. Still, I’d strongly consider a single DDR5 DIMM if you’ve been eyeing an LGA 1700 platform with DDR4, assuming you’re primarily focused on gaming.
Starfield shows the benefits of 3D V-Cache in this single-DIMM configuration clearly. While the performance losses with other CPUs are brutal in this title, the 9800X3D dropped just a few frames, a 1.6% decrease in average performance.
(Image credit: Tom's Hardware)
Doom: The Dark Ages is similarly harsh on single-DIMM configurations. The Ryzen 5 7600X dropped 17.3% of its average performance, and the 270K Plus fell by 14%. The 9800X3D holds up well, however, with just a 4.2% average performance loss. Marvel’s Spider-Man 2 (in the gallery below) shows a similar dynamic.
(Image credit: Tom's Hardware)
However, the addition of 3D V-Cache mainly helps in these games where we see bigger losses with other CPUs. There are several games in our suite where the performance loss between a single DIMM and dual-channel configuration was minor, particularly in GPU-heavy titles. The Last of Us Part One shows that in action.
(Image credit: Tom's Hardware)
Similarly, the performance loss is minor in Counter-Strike 2, just a handful of frames even north of 600 FPS. Even the Core i5-14600K, which was hit the hardest by far, dropped just 5.9% of its average performance (and it’s still faster than a dual-channel DDR4 configuration).
You can browse the results of the other games we tested in the gallery above, though they tell much the same story as the titles we highlighted. The two biggest learnings from this testing are that a single, fast DDR5 DIMM often outpaces dual-channel DDR4, and that AMD’s 3D V-Cache can smooth over the rough edges of using a single DIMM, particularly in those memory-sensitive titles.
How we tested
We tested on our normal test bed that we use for CPU reviews, with the only difference being dropping one of our DIMMs. As usual, we enabled XMP/EXPO for testing, both on single- and dual-DIMM configurations, opting for higher speeds on Intel platforms. AMD’s sweet spot is around 6,000 MT/s.
The data rate is noteworthy for the DDR4 comparison, in particular. With slower DDR5, we expect the delta between dual-channel DDR4 and single-DIMM DDR5 to decrease.
In addition to enabling XMP/EXPO, we disable Virtualization-Based Security (VBS), enable Resizeable BAR, and disable any automatic overclocking features that aren’t covered by warranty, including AMD’s Precision Boost Overdrive and Intel’s Extreme performance profile.
DDR5 has much higher data rates compared to DDR4 (2x or more), and that’s the result of significantly more complexity on DDR5 DIMMs compared to DDR4. Notably for this testing are the two 32-bit subchannels of DDR5, as well as enlarged prefetch and bank groups. You are getting half the total bandwidth with a single DDR5 DIMM, absolutely, but it’s a little more nuanced than simply running your memory in a single-channel configuration.
DDR4 uses a single 72-bit channel, and 64 of those bits transfer data (the additional 8 are for ECC). With DDR5, you get two 40-bit subchannels, 32 of which are used for data transfer. Critically, these subchannels have their own Command/Address (CA) interface, allowing them to operate independently of each other.
In addition, DDR5 doubles the prefetch size to 16N, doubles the number of banks and bank groups, and increases burst length from 8 bytes to 16 bytes. The math here is straightforward enough. With DDR4, you can transfer 64 bits of data over the interface at a burst of 8 bytes, giving you 64 bytes of data and aligning with cache line sizes. Each of the subchannels in DDR5 can transfer 64 bytes of data, as well, with a 32-bit width and burst length of 16 bytes.
It’s pseudo-dual-channel memory on a single DIMM. There are two independent memory operations that can happen each cycle, both of which transfer 64 bytes of data. That is a big reason why even a single DDR5 DIMM (particularly one with a higher data rate) can outpace even a proper dual-channel DDR4 configuration.
The common wisdom about using a single DIMM comes mainly from previous DDR generations, where you can only get that single 64-byte transfer each cycle, necessitating a second DIMM to have two independent operations.
Let me be clear: two DDR5 DIMMs are still better. Instead of two operations per cycle, you can perform four. The main difference is that, for modern CPUs and games, just those two operations give you the vast majority of your performance, and you don’t run into a massive performance bottleneck as you do with just a single operation via DDR4. After all, there are still a lot of DDR4 systems out there.
On the issue of compatibility
The elephant in the room with upgrading to a DDR5 platform with a single DIMM is compatibility. If you get a single DDR5 DIMM now, you should plan to add another in the future. Unfortunately, there aren’t a lot of easy answers when it comes to combining two DIMMs that aren’t in a kit together. It should work, but mixing and matching can lead to stability issues and/or lowered performance.
Generally, combining two DIMMs of the same spec should work. For instance, if you bought this Patriot Viper Venom DDR5-6000 CL30 DIMM to start your new build, and then bought a second one later, it should work. “Should” carries a lot of weight on its shoulders, however. Maybe Patriot sources DRAM from multiple places, or your second DIMM’s timings don’t completely align with your first. That could cause stability or performance issues.
There have been some attempts to get past this hurdle, such as the ROG Certified program with select Asus motherboards, but it’s impossible to know for sure if two separate DIMMs will work together or not without testing. The best you can do is to make sure you buy the same brand of memory, with the same spec, if you add a second DIMM. Make sure to keep your receipt handy in the event you need to return it, as well.
Once you have your second DIMM, make sure to test it first at stock JEDEC speeds/timings (no XMP/EXPO). Run games or applications you normally run, and then use a utility like MemTest64 to check for stability. I’d recommend keeping your PC running in this state for a few days to see if any BSODs, application crashes, or poor performance issues pop up. After that’s done, repeat the process with XMP/EXPO enabled, assuming you’re using matching DIMMs (incompatible XMP/EXPO profiles won’t work together).
Assuming DRAM prices continue at an elevated rate before you upgrade, you may want to consider investing in a dual-channel kit down the line and selling your single DIMM. Even kits can run into compatibility issues, though the likelihood is far, far lower.
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